CIRCUIT DESIGNER PRO
Design Mode
CIRCUIT DESIGNER PRO
DIGITAL CIRCUIT DESIGN & DEBUG
SEQUENTIAL MODE
▶ STEP
AUTO CLK
↺
RESET
WAVEFORM
MEM
PIPE
STEP: 0
SPEED
600ms
BIN
DEC
HEX
EXAMPLES
↶
↷
?
OTHER
PIPELINE
CPU
MEMORY
BLOCKS
LOGIC
MUX
DEMUX
DECODER
ENCODER
H-ADD
F-ADD
CMP
BMUX
SEXT
SPLIT
MERGE
AND
OR
XOR
NAND
NOR
XNOR
NOT
BUF
TRI
D-FF
T-FF
SR-FF
JK-FF
D-LATCH
SR-LATCH
ALU
IR
CU
BUS
IMM
PIPE
HS
REG
SHREG
CNT
RAM
ROM
RF
RF-DP
FIFO
STACK
PC
SW
7SEG
IN
OUT
WIRE
CLK
DESIGN TOOLS
SELECT
MULTI-SELECT
DELETE
PROPERTIES
Label
Value
0
Steps
Value
0
Steps
Init Q
0
Size
2
4
8
16
Bit Width
1
2
4
8
16
32
64
Addr Bits
1
2
3
4
5
6
8
12
16
24
Control
+ STALL
+ FLUSH
WIRE PROPERTIES
Net Name
Color
Auto
Red
Green
Blue
Yellow
Purple
Orange
Cyan
Pink
Clock Wire
OFF
RESET ROUTE
EXPORT
IMPORT
SCREENSHOT
CLEAR ALL
BREAKPOINTS
+ ADD ON SELECTED
CLEAR ALL
WAVEFORM
⌃+scroll zoom · drag to pan · F to fit
◨ SIGNALS
+
BMK
TRIG
DEC
FIT
⛶ FULL
.VCD
IMPORT
.PNG
CLOSE
DEBUG
CLOSE
WATCH LIST
+ WATCH SELECTED
CLEAR
DIAGNOSTICS
enabled
SIGNAL TRACE
TRACE FORWARD →
← TRACE BACKWARD
STOP TRACE
TRUTH TABLE
GENERATE
MEMORY INSPECTOR
DEC
CLOSE
PIPELINE
STAGES
RETIME
REFRESH
CLOSE
DEBUG
⇤
↔
⇥
⇡
↕
⇣
☰H
☰V
CREATE BLOCK
SAVE PROJECT
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Properties
Duplicate
Center View
Debug
View Internals
Expand Block
Copy
Paste
Bring to Front
Send to Back
Disconnect All
Delete
KEYBOARD SHORTCUTS
CLOSE
CONTROL UNIT — OPCODE TABLE
Opcodes:
4
8
16
32
64
128
256
RESET DEFAULT
SAVE
CLOSE
OP
NAME
ALU_OP
REG_WE
MEM_WE
MEM_RE
JMP
HALT
IMM
HEX
ROM EDITOR
C
ASM
TABLE
LOAD FILE
SAVE
CLOSE
ADDR
HEX
ASSEMBLY
INSERT
RETIME SUGGESTION
Reject
Accept
Pipeline balanced.
Press Ctrl+Z to undo
EXAMPLES
CLOSE